Home > CompTIA Network+ Certification Exam > Quizzes > Digital Logic Circuits (DLC) Practice Test
Digital Logic Circuits (DLC) Practice Test
Fast practice, instant feedback. Timer auto-submits when time’s up.
Avg score: 100% Most missed: “A disadvantage of DTL is _____________”
A Digital Logic Circuits (DLC) uses digital inputs to make logical decisions and produce digital outputs. Every logic circuit requires at least one input, before it can produce any kind of output. Digital logic inputs and outputs are usually binary - there can only be one of two possible values. There are two basic types of logic circuitry: combinational circuitry and state circuitry. Combinational circuitry behaves like a simple function. The output of combinational circuitry depends only on the current values of its input. State circuitry behaves more like an object method. All digital... Show more
Digital Logic Circuits (DLC) Practice Test
Time left 00:00
25 Questions

1. Let A and B is the input of a subtractor then the borrow will be _____________
2. In gated D latch, which of the following is the input symbol?
3. In serial shifting method, data shifting occurs _____________.............
4. The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called
5. The S-R, J-K and D inputs are called _____________.............
6. Shift registers comprise of which flip-flops?
7. The number of logic gates and the way of their interconnections can be classified as
8. 29 input circuit will have total of _____________.............
9. A technique used to reduce the magnitude of threshold voltage of MOSFET is the
10. How many flip-flops are in the 7475 IC?
11. Perform multiplication of the binary numbers: 01001 × 01011 = ?
12. A shift register is defined as _____________
13. How can parallel data be taken out of a shift register simultaneously?
14. Which of the following best describes the fusible-link PROM?
15. The asynchronous input can be used to set the flip-flop to the _____________.............
16. UP-DOWN counter is a combination of _____________.............
17. ‘shift_reg’ is used to initialize the
18. Three decade counter would have _____________.............
19. The difference between half adder and full adder is _____________
20. Critical defects per unit chip area is for a MOS transistor.
21. Total number of inputs in a half adder is _____________
22. A ripple counter’s speed is limited by the propagation delay of _____________.............
23. Synchronous counter use global clock, unlike asynchronous counter.
24. How much locations an 8-bit address code can select in memory?
25. How many types of sequential circuits are?