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Computer Organization and Architecture: Memory Organization
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Computer Organization and Architecture: Memory Organization
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20 Questions

1. Cache Memory is implemented using the DRAM chips.
2. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.
3. Which of the following is independent of the address bus?
4. What is the high speed memory between the main memory and the CPU called?
5. LRU stands for ___________
6. Which of the following is an efficient method of cache updating?
7. If M denotes the number of memory locations and N denotes the word size, then an expression that denotes the storage capacity is ______________
8. Which of the following is independent of the address bus?
9. LRU stands for ___________
10. Size of the ________ memory mainly depends on the size of the address bus.
11. The transfer between CPU and Cache is ______________
12. MAR stands for ___________
13. Cache memory is the onboard storage.
14. What is the location of the internal registers of CPU?
15. Which of the following is an efficient method of cache updating?
16. Any electronic holding place where data can be stored and retrieved later whenever required is ____________
17. Cache Memory is implemented using the DRAM chips.
18. In ____________ mapping, the data can be mapped anywhere in the Cache Memory.
19. When the data at a location in cache is different from the data located in the main memory, the cache is called _____________
20. The transfer between CPU and Cache is ______________

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