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Digital System Design: Logic Family and Logic Gates
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Digital System Design: Logic Family and Logic Gates
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25 Questions

1. (A + B)(A' * B') = ?
2. According to boolean law: A + 1 = ?
3. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
4. The speed of ______ circuits is limited by the tendency of common emitter circuits to go into saturation.
5. The full form of CMOS is ____________
6. When is a level-shifter circuit needed in interfacing logic? 
7. The following switching functions are to be implemented using a decoder:
8. TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
9. A universal logic gate is one which can be used to generate any logic function. Which of the following is a universal logic gate?
10. The boolean function A + BC is a reduced form of ____________
11. The output will be a LOW for any case when one or more inputs are zero in a/an '
12. The NOR gate output will be high if the two inputs are __________
13. The full form of TCTL is ____________
14. The following switching functions are to be implemented using a decoder: 1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
15. An open collector output can ________ current, but it cannot ________.
16. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
17. TTL devices consume substantially ______ power than equivalent CMOS devices at rest.
18. The inverter is......
19. A single transistor can be used to build '
20. An important characteristic of a CMOS circuit is the ____________
21. If all inputs to a TTL NAND gate are low, what is the ON, OFF condition of each transistor in the circuit?
22. Using the schematic diagram of a TTL NAND gate, determine the state of each transistor (ON or OFF) when all inputs are high.
23. Which chip were the first RTC and CMOS RAM chips to be used in early IBM computers, capable of storing a total of 64 bytes?
24. What is the advantage of using low-power Schottky (LS) over standard TTL logic?
25. The gates required to build a half adder are __________

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