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Digital System Design: Sequential Logic Circuit
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Digital System Design: Sequential Logic Circuit
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25 Questions

1. One example of the use of an S-R flip-flop is as ____________
2. In a 3-bit asynchronous down counter, the initial content is ____________
3. In D flip-flop, D stands for _____________
4. A down counter using n-flip-flops count ______________
5. A ripple counter's speed is limited by the propagation delay of _____________
6. In a 3-bit asynchronous down counter, at the first negative transition of the clock, the counter content becomes ____________
7. Both the J-K & the T flip-flop are derived from the basic _____________
8. Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?
9. A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates?
10. In J-K flip-flop, the function K=J is used to realize _____________
11. On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when ________
12. The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the _____________
13. A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ____________
14. A D flip-flop can be constructed from an ______ flip-flop.
15. When a high is applied to the Set line of an SR latch, then ___________
16. A ripple counter's speed is limited by the propagation delay of ____________
17. Three cascaded decade counters will divide the input frequency by ____________
18. When both inputs of SR latches are high, the latch goes ___________
19. With regard to a D latch ________
20. What does the triangle on the clock input of a J-K flip-flop mean?
21. A principle regarding most display decoders is that when the correct input is present, the related output will switch ____________
22. Why latches are called a memory devices?
23. The truth table for an S-R flip-flop has how many VALID entries?
24. UP Counter is ____________
25. Which statement describes the BEST operation of a negative-edge-triggered D flip-flop?

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