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Multi-core Architectures and Programming Practice Test: Multi-core Processors
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Multicore Architecture refers to an architecture in which a single physical processor incorporates the core logic of more than one processor. A single integrated circuit is used to package or hold these processors. These single integrated circuits are known as a die.
 

Multicore programming has multiple system tasks executing in parallel.

Types of parallelism include: Data parallelism. Task parallelism.

Multi-core Architectures and Programming Practice Test: Multi-core Processors
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23 Questions

1. The expression 'delayed load' is used in context of
2. If no node having a copy of a cache block, this technique is known as ______
3. Which cache miss does not occur in case of a fully associative cache?
4. Cache coherence: For which shared (virtual) memory systems is the snooping protocol suited?
5. The idea of cache memory is based ______
6. A collection of lines that connects several devices is called ______________
7. The concept of pipelining is most effective in improving performance if the tasks being performed in different stages :
8. Which MIMD systems are best scalable with respect to the number of processors?
9. When number of switch ports is equal to or larger than number of devices, this simple network is referred to as ______________
10. PC Program Counter is also called ____________
11. A remote node is being node which has a copy of a ______________
12. Parallel programs: Which speedup could be achieved according to Amdahl´s law for infinite number of processors if 5% of a program is sequential and the remaining part is ideally parallel?
13. During the execution of the instructions, a copy of the instructions is placed in the ______ .
14. A pipeline is like _______________
15. SIMD represents an organization that ______________
16. Systems that do not have parallel processing capabilities are ______________
17. All nodes in each dimension form a linear array, in the __________.
18. Requesting node sending the requested data starting from the memory, and the requestor which has made the only sharing node, known as ________.
19. Cache memory works on the principle of ____________
20. Alternative way of a snooping-based coherence protocol, is called a ____________
21. Bus switches are present in ____________
22. A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______.
23. In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data or instructions is ________________

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