Which of the following is also known as equivalence checker?

Formal verification is a process that uses mathematical methods to check if embedded system software models and code behave correctly. It can be used on models, generated code, and hand code.  Formal verification is mainly used during the design and development stages of software. It can: Identify errors in models Generate test vectors that reproduce errors in simulation Detect and prove the absence of run-time errors in source code Check compliance to coding standards Review code complexity metrics Measure software quality  Formal verification enables a designer to directly analyze... Show more

Formal verification is a process that uses mathematical methods to check if embedded system software models and code behave correctly. It can be used on models, generated code, and hand code. 

Formal verification is mainly used during the design and development stages of software. It can:
Identify errors in models
Generate test vectors that reproduce errors in simulation
Detect and prove the absence of run-time errors in source code
Check compliance to coding standards
Review code complexity metrics
Measure software quality 

Formal verification enables a designer to directly analyze and mathematically explore the quality or other aspects of a Register Transfer Level (RTL) design without using simulations. 

Subareas of formal verification include:
Deductive verification
Abstract interpretation
Automated theorem proving
Type systems
Lightweight formal methods 

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