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VLSI Design & Technology
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VLSI Design & Technology
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25 Questions

1. Which among the following operation/s is/are executed in physical design or layout synthesis stage?
2. The output of sequential circuit is regarded as a function of time sequence of __________. A. Inputs B. Outputs C. Internal States D. External States
3. The utilization of CAD tools for drawing timing waveform diagram and transforming it into a network of logic gates is known as ________.
4. An event is nothing but ______ target signal, which is to be updated.
5. Which among the following constraint/s is/are involved in a state-machine description?
6. The time required for an input data to settle _____ the triggering edge of clock is known as ‘Setup Time’.
7. In DIBL, which among the following is/are regarded as the source/s of leakage?
8. In composite data type of VHDL, the record type comprises the elements of _______data types.
9. Which among the following is/are identical in Mealy & Moore machines?
10. _________ is the fundamental architecture block or element of a target PLD.
11. In signal integrity, which noise/s occur/s due to impedance mismatch, stubs, vias and other interconnection discontinuities?
12. Which concept proves to be beneficial in acquiring concurrency and order independence?
13. Which type of CPLD packaging comprises pins on all four sides that wrap around the edges of chip?
14. An Antifuse programming technology is predominantly associated with _____.
15. In accordance to the scaling technology, the total delay of the logic circuit depends on ______
16. The devices which are based on fusible link or antifuse are _________time/s programmable.
17. Maze routing is used to determine the _______path for a single wire between a set of points, if any path exists.
18. On the basis of an active load, which type of inverting CMOS amplifier represents low gain with highly predictable small and large signal characteristics?
19. In VHDL, which class of scalar data type represents the values necessary for a specific operation?
20. In logic synthesis, ________ is an EDIF that gives the description of logic cells & their interconnections.
21. If the level of fan-out is beyond a limit in synthesis, it results in an insertion of buffer by ultimate effect of _____ the speed.
22. Which level of routing resources are supposed to be the dedicated lines allowing output of each tile to connect directly to every input of eight surrounding tiles?
23. Which type of simulator/s neglect/s the intra-cycle state transitions by checking the status of target signals periodically irrespective of any events?
24. An Assert is ______ command.
25. In MOS devices, the current at any instant of time is ______of the voltage across their terminals.

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