1. The SCSI BUS is used to connect the video devices to a processor by providing a ______________.

2. CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged.

3. The advantage of I/O mapped devices to memory mapped is ___________

4. In DMA transfers, the required signals and addresses are given by the __________

5. In memory-mapped I/O ____________

6. ______ type circuits are generally used for interrupt service lines.
i. open-collector
ii. open-drain
iii. XOR
iv. XNOR

7. The starting address sent by the device in vectored interrupt is called as __________

8. A single Interrupt line can be used to service n different devices.

9. The signal sent to the device from the processor to the device after receiving an interrupt is ___________

10. From amongst the following given scenarios determine the right one to justify interrupt mode of data transfer.
i. Bulk transfer of several kilo-byte
ii. Moderately large data transfer of more than 1kb
iii. Short events like mouse action
iv. Keyboard inputs

11. ______________ register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt.

12. The signal sent to the device from the processor to the device after receiving an interrupt is ___________

13. The controller is connected to the ____

14. The usual BUS structure used to connect the I/O devices is ___________

15. Interrupts initiated by an instruction is called as _______

16. The code sent by the device in vectored interrupt is _____ long.

17. Which table handle stores the addresses of the interrupt handling sub-routines?

18. Which one of the following is true with regard to a CPU having a single interrupt request line and single interrupt grant line?
i. Neither vectored nor multiple interrupting devices is possible.
ii. Vectored interrupts is not possible but multiple interrupting devices is possible.
iii. Vectored interrupts is possible and multiple interrupting devices is not possible.
iv. Both vectored and multiple interrupting devices are possible.

19. An interrupt that can be temporarily ignored is ___________

20. The ISA is an architectural standard developed by ______.

21. When the process is returned after an interrupt service ______ should be loaded again.
i. Register contents
ii. Condition codes
iii. Stack contents
iv. Return addresses

22. The 8085 microprocessor responds to the presence of an interrupt ___________

23. In vectored interrupts, how does the device identify itself to the processor?

24. To overcome the conflict over the possession of the BUS we use ______

25. The DMA differs from the interrupt mode by __________